1. Field of the Invention
The present invention relates to a contact sheet for testing electronic parts such as semiconductor wafers, semiconductor chips, BGA (Ball Grid Allay) packages and passive elements, a test apparatus having a contact sheet, and a test method using this test apparatus, electronic parts manufacturing method, and electronic parts.
2. Description of the Related Art
With the miniaturization and simplification of the semiconductor package, KGD (Known Good Die) technology to detect good or bad of each chip is needed when many chips are mounted on a single package such as MCM (Multi Chip Module) or for the bear die supply of COB (Chip On Board).
Conventionally, after a semiconductor chip is mounted on a package substrate, a test substrate such as a hard testing multilayer substrate is pressed against the OLB terminal or the electrodes of the semiconductor chip or wafer to electrically contact so to conduct a test. At this time, the electrodes of the electronic parts such as the semiconductor chip or the semiconductor wafer are contacted to the substrate electrodes of the test substrate. The test apparatus has the test substrate and the test circuit and also has wiring for electrical connection between the test substrate and the test circuit. Where a BGA package is subject to a burn-in test or the like, a BGA ball package is placed in a dedicated socket which is electrically connected to the test circuit and contacted under pressure for testing. In using the wafer or the like, a probe is pressed against the electrodes of the wafer.
The test includes, for example, a high-temperature bias test. This test exposes a device to a high-temperature atmosphere while applying a voltage. This test is an acceleration test simulating actual busy conditions and can provide a test result in a short time by physically and temporally accelerating the cause of deterioration. This test is used as part of a life test involved in screening (or the burn-in test) for removal of an initial failure and reliability tests.
As to the burn-in test for a wafer level, there is a known test apparatus (see Japanese Patent Laid-Open Application No. Hei 10-284556) that a wafer is held on a base with the element surface having the electrodes formed upward, and that comprises a multilayer sheet which has protruded electrodes in positions to face the electrodes of the wafer, flexible members having conductivity in positions to face the electrodes, a burn-in base material unit having high flatness and wiring to the test circuit, and a mechanism for applying a pressure.
Conventional technology having a porous resin disposed between an insulating substrate and a semiconductor chip of a semiconductor package and maintaining their joined state in a good condition is also known (see Japanese Patent Laid-Open Application No. Hei 11-163203). Technology of forming via or wiring within the porous body of an insulating material such as a liquid crystalline polymer including polytetrafluoroethylene, polyimide and aramid is known (see Japanese Patent Laid-Open Applications No. 2001-345537 and No. 2001-83347).
When the electrodes (e.g., solder bumps) of a semiconductor chip or the like are soldered to a hard test substrate, the electrodes of the semiconductor chip or the test substrate are broken or the solder bumps are broken at any part when the semiconductor chip is removed from the test substrate, so that it is hard to control such damage. Therefore, the burn-in test or the like is conducted with the electrodes or terminals of a package or a chip pressed against the test substrate. In such a case, the test apparatus requires a mechanism to pressurize and hold electronic parts such as a semiconductor chip other than an aligning mechanism.